Regviz

Cypress Semiconductor /psoc63 /BLE /RCB /TX_CTRL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as TX_CTRL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Cypress Semiconductor/psoc63/BLE/RCB/TX_CTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MSB_FIRST)MSB_FIRST 0 (FIFO_RECONFIG)FIFO_RECONFIG 0TX_ENTRIES

Description

Transmitter control register.

Fields

MSB_FIRST

Least significant bit first (‘0’) or most significant bit first (‘1’). This field also affects the Address field When MSB_FIRST = 1, then [15:0] is data and [(ADDR_WIDTH+15):16] is used for address When MSB_FIRST = 0, then [15:0] is for data. No address field
FIFO_RECONFIG

Setting this bit, clears the FIFO and resets the pointer
TX_ENTRIES

This field determines the depth of the TX_FIFO. Allowed legal values are 8 and 16 only

Links

()

Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data